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The control cycle

This page is being written

The cycle itself is decided and stated below. The numbers, the tuning and the worked examples are still to come.

The cycle is the classic one:

  1. Read inputs into a process image.
  2. Run the logic, working only on that snapshot.
  3. Write outputs.
  4. Wait for the rest of the period.

Logic never touches the hardware directly. It sees a snapshot taken at the top of the cycle and nothing else, which is what makes a run reproducible.

Timing

To be written.

Why timers are counted in milliseconds

A timer that counts cycles drifts as soon as the cycle jitters. Every timer in the block library works from a monotonic millisecond clock instead, so a delay is a delay whatever the load.

What happens under load

To be written. Covers the degradation rule — logic, then communication, then graphics — and what is dropped first.

What never runs inside the cycle

To be written. Covers: bus pollers run outside it, so a slow or unreachable device cannot stretch it; parameter writes to a drive happen at start-up, never per cycle.